;;; -*- Mode: Midas -*-
;;; Copyright (c) 1999 Massachusetts Institute of Technology
;;;
;;; This program is free software; you can redistribute it and/or
;;; modify it under the terms of the GNU General Public License as
;;; published by the Free Software Foundation; either version 3 of the
;;; License, or (at your option) any later version.
;;;
;;; This program is distributed in the hope that it will be useful,
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
;;; General Public License for more details.
;;;
;;; You should have received a copy of the GNU General Public License
;;; along with this program; if not, see https://gnu.org/licenses or
;;; write to:
;;;  Free Software Foundatiom, Inc.
;;;  51 Franklin St, Fifth Floor
;;;  Boston, MA 02110-1301
;;;  USA

.AUXIL

;;; Canonical symbol definition macro, FOO==BAR with error check.
IFNDEF DEFSYM,[	
DEFINE DEFSYM X/
IRPS Z,,[X]
IFNDEF Z,X
.ELSE [	$$TEM1==Z
	X
	IFN Z-$$TEM1,.ERR Z MULTIPLY .QUOTE`.QUOTE/DEFINED/`
      ]
.ISTOP
TERMIN TERMIN
$$TEMP==1
] ;IFNDEF DEFSYM
.ELSE, $$TEMP==0

; The ACC IMP interface on the KS implements two separate Unibus IO
; devices, for input and output. Both of these devices transfer data in
; 32-bit mode only over the Unibus via DMA.  Because of the DMA data
; transfer the interrupt structure is trivial, and uses NETCHN only.
;
; Apparently the reset bits in the two CSRs are wired together, so
; resetting one side of the machine resets both. This action also drops
; the HOST READY line to the IMP.
;
; You must set %LHSE whenever hte HOST READY line is high, or the IMP
; will be allowed to freely throw away data. This is true across IMP
; message boundaries, and even if no input request is active.
; 

;ACC LH-DH IMP Interface Bits

;Interrupt information
DEFSYM	%LHVEC==250		;Input side interrupt vector (non-standard)
				;Output side assumed to be %LHVEC+4
DEFSYM	%LHPRI==6		;Interrupt priority (non-standard)

DEFSYM	%LHBAS==767600		;Base of LH/DH Unibus register address space

;Unibus Registers
DEFSYM	%LHICS==%LHBAS		;Control and Status, Input side
DEFSYM	%LHIDB==%LHBAS+2	;Data Buffer, Input
DEFSYM	%LHICA==%LHBAS+4	;Current Word Address, Input
DEFSYM	%LHIWC==%LHBAS+6	;Word Count, Input

DEFSYM	%LHOCS==%LHBAS+10	;Control and Status, Output side
DEFSYM	%LHODB==%LHBAS+12	;Data Buffer, Output
DEFSYM	%LHOCA==%LHBAS+14	;Current Word Address, Output
DEFSYM	%LHOWC==%LHBAS+16	;Word Count, Output

;Bits in CSRs
; Bits common to input and output
DEFSYM	%LHERR==1_15.		;Error present
DEFSYM 	%LHNXM==1_14.		;Non Existant Memory on DMA
DEFSYM	%LHMRE==1_9.		;Master Ready Error (ready bounce during xfr)
DEFSYM	%LHRDY==1_7.		;Device Ready (modifying LHDH regs allowed)
DEFSYM	%LHIE==1_6.		;Interrupt Enable
DEFSYM	%LHA17==1_5.		;Address bit 17 for extended unibus xfrs
DEFSYM	%LHA16==1_4.		;Address bit 16 for extended unibus xfrs
DEFSYM	%LHRST==1_1.		;Interface Reset
DEFSYM	%LHGO==1		;GO - Start DMA Transfer

; Input side
DEFSYM	%LHEOM==1_13.		;End-of-Message received from IMP
DEFSYM	%LHHR==1_11.		;Host Ready (ACC's relay closed, debounced)
DEFSYM	%LHINR==1_10.		;IMP not ready
DEFSYM	%LHIBF==1_8.		;Input Buffer Full
DEFSYM	%LHSE==1_3.		;Store Enable (0 == flush data instead)
DEFSYM	%LHHRC==1_2.		;Host Ready Relay Control (1 to close relay)

; Output side
DEFSYM	%LHWC0==1_13.		;Output Word Count is zero
DEFSYM	%LHOBE==1_8.		;Output Buffer Empty
DEFSYM	%LHBB==1_3.		;Bus Back (loopback enable for testing)
DEFSYM	%LHELB==1_2.		;Send EOM indication to IMP at end of xfr
				; (enable Last Bit Flag)
IFN $$TEMP,EXPUNG DEFSYM

